Toshiba has unveiled its newly developed Flip-Flop circuit configuration using 40nm CMOS process which company claims would reduce power consumption in mobile equipment. For example, the measure data that has been recorder when the new configuration has been applied to wireless LAN verifies that the power dissipation of the new flip-flop is up to 77% less than conventional flip-flop, furthermore, it achieves a 24% reduction in overall power consumption. As an essential part a SoC design, a flip-flop is a circuit that temporarily stores one bit of data during arithmetic processing by a SoC which is incorporated within mobile equipment as well as other digital equipment. Normally, is responsible to incorporate a clock buffer to produce a clock inverted signal required for operation of circuit. The clock buffer consumes power when triggered by a signal from the clock, even when data is not changed. In order to reduce this power dissipation, a power saving technique by the name of clock gating is used in order to cut delivery of clock signal to unused blocks; however by applying this power saving technique, the flip-flop active rate is only 5-15%, leaving room for further power reduction. To further reducing the power consumption, Toshiba has changed the structure of the conventional flip-flop and has eliminated the clock buffer all together.
This approach, would normally, causes data collision between data writing circuitry and the state holding circuitry in the flip-flop, but Toshiba has overcome this issue through addition of adaptive coupling circuitry , combination of an nMOS and a pMOS transistors to the flip-flop, which results in weakening of state-retention coupling and prevents collisions. In spite of the addition of adaptive coupling circuitry, the transistor count has been reduced from 24 to 22, making the cell area smaller that of the conventional flip-flop.
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